Hardware IP for Scheduling of Periodic tasks in Multiprocessor Systems
نویسندگان
چکیده
The article presents an Intellectual Property (IP) for scheduling of multiprocessor systems that is designed using FPGA. The purpose of the IP is to minimize the processor time for scheduling activity by implementing the functionality in hardware. The algorithm implemented clusters the similar tasks on the same processor. Processors not in use are switched to power saving mode and they are only turned on if there is no other processor to take on the required activity. Key-words: FPGA, Hardware scheduler, multiprocessor systems, real-time systems, scheduling algorithm.
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